Integrated circuits may fail in a variety of ways, and with memories continuing to be more common as at least a portion of integrated circuits, failures in memories are having a bigger impact. One of the failures in memories relates to addressing errors related to wordlines.
U.S. Pat. No. 8,379,468 describes embodiments that detect an address fault where no wordline is enabled when the memory is intended to be accessed. Detection for this type of failure is indicated by a wordline on indicator signal that indicates whether at least one wordline has been enabled. This patent also describes embodiments that detect an address fault where more than one wordline is enabled in the same array or sub-array. The signal that indicates this type of fault is a multi-wordline on fault indicator signal. As described in this patent, although it is preferable that address fault errors do not occur, it is useful to detect address faults and provide a fault indication as quickly as possible.
FIG. 1 (Prior Art) is a block diagram from U.S. Pat. No. 8,379,468 providing a memory system 10 including an address ROM (read only memory) 20 and detection logic 22 that are used to generate a wordline on indicator and a multi-wordline on indicator. Memory system 10 includes an address decoder 11 coupled to receive an address, a wordline driver 12 coupled to address decoder 11, column logic 16, and control logic 14 coupled to address decoder 11, wordline driver 12, and column logic 16. The memory system 10 also includes a data array 18 of memory cells coupled to wordline driver 12, control logic 14, and column logic 16. The address ROM 20 is coupled to data array 18, and the detection logic 22 is coupled to address ROM 20. Control logic 14 receives a write/read (WR/RD) signal, a clock (CLK), and an enable signal. Column logic 16 inputs data in and outputs data out. Column logic 16 may also receive address information. Detection logic 22 receives clock (CLK) and outputs the wordline on indicator and the multi-wordline on indicator.
In operation, as described in U.S. Pat. No. 8,379,468, control logic 14 receives the enable signal, and address decoder 11 responds to the address as timed by the clock (CLK) to select a wordline in data array 18. Wordline driver 12 enables the selected wordline. When a wordline is enabled, it is considered on. When write/read signal (WR/RD) is for a write, data in is written into memory cells along the selected wordline by column logic 16. When signal WR/RD is for a read, column logic outputs data out from the memory cells along the enabled wordline. Address ROM 20, being coupled to the wordlines of data array 18, detects the presence or absence of signals on the wordlines as further described in U.S. Pat. No. 8,379,468, and couples that information to detection logic 22. Detection logic 22 interprets the information and provides the wordline on indicator and multi-wordline on indicator accordingly.
While the embodiments described in U.S. Pat. No. 8,379,468 are effective solutions for detecting wordline on and multi-wordline on address faults, there is still a need for additional solutions for the rapid detection of address faults in memory array systems.